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JSA
2008
94views more  JSA 2008»
13 years 7 months ago
Energy reduction through crosstalk avoidance coding in networks on chip
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cri...
HPCA
2008
IEEE
14 years 8 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
WMPI
2004
ACM
14 years 1 months ago
SCIMA-SMP: on-chip memory processor architecture for SMP
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, ...
DAC
2001
ACM
14 years 8 months ago
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...
IEEEPACT
2009
IEEE
13 years 5 months ago
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
Carlos Luque, Miquel Moretó, Francisco J. C...