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    SENSYS
    2009
    ACM
    175views Sensor Networks» more  SENSYS 2009»
    Low-power clock synchronization using electromagnetic energy radiating from AC power lines
    14 years 5 months ago
    Low-power clock synchronization using electromagnetic energy radiating from AC power lines
    Download  www.andrew.cmu.edu
    Clock synchronization is highly desirable in many sensor networking applications. It enables event ordering, coordinated actuation, energy-efficient communication and duty cyclin...
    Anthony Rowe, Vikram Gupta, Ragunathan Rajkumar
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    DATE
    2005
    IEEE
    154views Hardware» more  DATE 2005»
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
    14 years 4 months ago
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
    Download  infoscience.epfl.ch
    We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
    Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...
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    ASPDAC
    2007
    ACM
    82views Hardware» more  ASPDAC 2007»
    Low-Power High-Speed 180-nm CMOS Clock Drivers
    14 years 2 months ago
    Low-Power High-Speed 180-nm CMOS Clock Drivers
    Download  www.cecs.uci.edu
    - The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
    Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobaya...
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    ISLPED
    2005
    ACM
    90views Hardware» more  ISLPED 2005»
    Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
    14 years 4 months ago
    Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
    Download  www.eecs.harvard.edu
    This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
    Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
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    TVLSI
    2002
    107views more  TVLSI 2002»
    Low-power clock distribution using multiple voltages and reduced swings
    13 years 10 months ago
    Low-power clock distribution using multiple voltages and reduced swings
    Download  www.ece.umn.edu
    : Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...
    Jatuchai Pangjun, Sachin S. Sapatnekar
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