14548 search results - page 2832 / 2910 » The Optimal Path-Matching Problem |
ICCAD
2005
IEEE
14 years 7 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...
ICCAD
2001
IEEE
14 years 7 months ago
2001
IEEE
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
SOSP
2009
ACM
14 years 7 months ago
2009
ACM
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
FPGA
2010
ACM
14 years 7 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...