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» The Power of Comparative Reasoning
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ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
14 years 3 months ago
A thread partitioning algorithm in low power high-level synthesis
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Ta...
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
14 years 3 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
14 years 3 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...
ISQED
2000
IEEE
91views Hardware» more  ISQED 2000»
14 years 2 months ago
Probabilistic Bottom-Up RTL Power Estimation
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
Ricardo Ferreira, A.-M. Trullemans, José C....
CHES
2006
Springer
74views Cryptology» more  CHES 2006»
14 years 1 months ago
Optically Enhanced Position-Locked Power Analysis
Abstract. This paper introduces a refinement of the power-analysis attack on integrated circuits. By using a laser to illuminate a specific area on the chip surface, the current th...
Sergei P. Skorobogatov