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ICISC
2009
125views Cryptology» more  ICISC 2009»
13 years 5 months ago
Power Analysis of Single-Rail Storage Elements as Used in MDPL
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
Amir Moradi, Thomas Eisenbarth, Axel Poschmann, Ch...
DATE
2002
IEEE
100views Hardware» more  DATE 2002»
14 years 27 days ago
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
14 years 4 months ago
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors
We preseM an algorithm for compiler-driven regisrer mme adjustment with rhe main goal of power minimization on instruction fetch und mgisterjile access. In mosr instruction set ar...
Peter Petrov, Alex Orailoglu
ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 1 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 1 months ago
Dynamic Functional Unit Assignment for Low Power
A hardware method for functional unit assignment is presented, based on the principle that a functional unit’s power consumption is approximated by the switching activity of its...
Steve Haga, Natasha Reeves, Rajeev Barua, Diana Ma...