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» The Power of the Middle Bit
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VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
14 years 8 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 4 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
ICC
2008
IEEE
122views Communications» more  ICC 2008»
14 years 2 months ago
Multi-Carrier Transmission with Limited Feedback: Power Loading over Sub-Channel Groups
— Feedback of channel state information (CSI) enables a multi-carrier transmitter to optimize the power allocation across sub-channels. We consider a single user feedback scheme ...
Manish Agarwal, Dongning Guo, Michael L. Honig
ICCAD
1999
IEEE
89views Hardware» more  ICCAD 1999»
14 years 9 days ago
A bipartition-codec architecture to reduce power in pipelined circuits
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-J...
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
14 years 5 hour ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...