1728 search results - page 10 / 346 » The Size of Power Automata |
ISLPED
1995
ACM
13 years 12 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
PATMOS
2007
Springer
14 years 2 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
ICCAD
1994
IEEE
14 years 17 days ago
1994
IEEE
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep tran...
ICCD
2002
IEEE
14 years 5 months ago
2002
IEEE
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...