100 search results - page 10 / 20 » The Sizing Rules Method for Analog Integrated Circuit Design |
TCAD
2002
13 years 8 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
TVLSI
2010
13 years 3 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
DSD
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...