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» The Sizing Rules Method for Analog Integrated Circuit Design
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DAC
2008
ACM
14 years 8 months ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel
ISQED
2007
IEEE
120views Hardware» more  ISQED 2007»
14 years 1 months ago
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, ...
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
14 years 25 days ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
WSC
2000
13 years 8 months ago
Using simulation to evaluate cargo ship design on the LPD17 program
As part of the design of the next generation Naval Amphibious Transport Dock Ship (LPD17), simulation was used to evaluate the arrangement and flow of cargo on the ship and to int...
Joseph Hugan
DAC
2010
ACM
13 years 8 months ago
Detecting tangled logic structures in VLSI netlists
This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can...
Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li...