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LCTRTS
2001
Springer
15 years 7 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
15 years 7 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
FPL
1999
Springer
74views Hardware» more  FPL 1999»
15 years 7 months ago
On Tool Integration in High-Performance FPGA Design Flows
Abstract. High-performance design flows for FPGAs often rely on module generators to counter coarse logic-block granularity and limited routing resources, However, the very flexi...
Andreas Koch
ISSS
1997
IEEE
142views Hardware» more  ISSS 1997»
15 years 7 months ago
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination
- An approach for broadband modem FIR filter design optimization is presented. It addresses the minimization of the number of addersubtractors used in the hardware implementation o...
Robert Pasko, Patrick Schaumont, Veerle Derudder, ...
DAC
1996
ACM
15 years 7 months ago
Issues and Answers in CAD Tool Interoperability
CAD tool interoperability issues are a recurring impediment to constructing a design methodology, especially if the methodology incorporates point tools from several vendors. Failu...
Mike Murray, Uwe B. Meding, Bill Berg, Yatin Trive...