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SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
14 years 4 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
SERP
2007
14 years 8 days ago
From Functional Requirements through Test Evaluation Design to Automatic Test Data Patterns Retrieval - a Concept for Testing of
- Functional testing of software dedicated for hybrid embedded systems should start at the early development phase and requires analysis of discrete and continuous signals, where t...
Justyna Zander-Nowicka, Abel Marrero Pérez,...
ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
14 years 4 months ago
Power-Time Tradeoff in Test Scheduling for SoCs
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
Mehrdad Nourani, James Chin
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
14 years 4 months ago
Reuse-based test access and integrated test scheduling for network-on-chip
In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test dat...
Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
ATS
2001
IEEE
137views Hardware» more  ATS 2001»
14 years 2 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu