48 search results - page 7 / 10 » The Validity of Retiming Sequential Circuits |
131
Voted
DATE
1997
IEEE
15 years 7 months ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
116
Voted
ICCD
2008
IEEE
16 years 18 days ago
2008
IEEE
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
136
Voted
ICCD
2001
IEEE
16 years 17 days ago
2001
IEEE
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
114
Voted
FCCM
2009
IEEE
15 years 10 months ago
2009
IEEE
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
114
Voted
VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...