Sciweavers

517 search results - page 36 / 104
» The design of a low energy FPGA
Sort
View
DAC
2002
ACM
14 years 9 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
GLOBECOM
2009
IEEE
14 years 3 months ago
Sparse Decoding of Low Density Parity Check Codes Using Margin Propagation
—One of the key factors underlying the popularity of Low-density parity-check (LDPC) code is its iterative decoding algorithm that is amenable to efficient hardware implementati...
Ming Gu, Kiran Misra, Hayder Radha, Shantanu Chakr...
ISLPED
2007
ACM
110views Hardware» more  ISLPED 2007»
13 years 10 months ago
A 0.4-V UWB baseband processor
A 0.4-V UWB digital baseband processor has been fabricated in a standard-VT 90-nm CMOS technology. The baseband processor operates at an ultra-low supply voltage to reduce energy ...
Vivienne Sze, Anantha P. Chandrakasan
SMI
2005
IEEE
14 years 2 months ago
Curvature-based Energy for Simulation and Variational Modeling
Curvature-based energy and forces are used in a broad variety of contexts, ranging from modeling of thin plates and shells to surface fairing and variational surface design. The a...
Denis Zorin
CORR
2010
Springer
133views Education» more  CORR 2010»
13 years 8 months ago
Scalable, Time-Responsive, Digital, Energy-Efficient Molecular Circuits using DNA Strand Displacement
We propose a novel theoretical biomolecular design to implement any Boolean circuit using the mechanism of DNA strand displacement. The design is scalable: all species of DNA stra...
Ehsan Chiniforooshan, David Doty, Lila Kari, Shinn...