517 search results - page 41 / 104 » The design of a low energy FPGA |
GLVLSI
2010
IEEE
13 years 10 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
— A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to f...
TASLP
2002
13 years 8 months ago
2002
When automatic speech recognition (ASR) and speaker verification (SV) are applied in adverse acoustic environments, endpoint detection and energy normalization can be crucial to th...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...