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» The energy complexity of register files
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ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
13 years 12 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
HPCA
2004
IEEE
14 years 8 months ago
Stream Register Files with Indexed Access
Many current programmable architectures designed to exploit data parallelism require computation to be structured to operate on sequentially accessed vectors or streams of data. A...
Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William ...
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
14 years 4 months ago
Making register file resistant to power analysis attacks
— Power analysis attacks are a type of side-channel attacks that exploits the power consumption of computing devices to retrieve secret information. They are very effective in br...
Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhiji...
ISLPED
1998
ACM
83views Hardware» more  ISLPED 1998»
13 years 11 months ago
A three-port adiabatic register file suitable for embedded applications
Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs...
Stephan Avery, Marwan A. Jabri
DATE
2009
IEEE
101views Hardware» more  DATE 2009»
14 years 2 months ago
Static analysis to mitigate soft errors in register files
—With continuous technology scaling, soft errors are becoming an increasingly important design concern even for earth-bound applications. While compiler approaches have the poten...
Jongeun Lee, Aviral Shrivastava