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ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 2 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 1 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
WCNC
2010
IEEE
13 years 6 months ago
Channel Modeling and MIMO Capacity for Outdoor Millimeter Wave Links
Recent work has shown that mesh networks based on short-range outdoor millimeter (mm) wave links in the unlicensed 60 GHz band are a promising approach to providing an easily deplo...
Hong Zhang, Sriram Venkateswaran, Upamanyu Madhow
DSN
2008
IEEE
14 years 3 months ago
An integrated approach to resource pool management: Policies, efficiency and quality metrics
: The consolidation of multiple servers and their workloads aims to minimize the number of servers needed thereby enabling the efficient use of server and power resources. At the s...
Daniel Gmach, Jerry Rolia, Ludmila Cherkasova, Gui...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 3 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...