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MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...