1476 search results - page 30 / 296 » Three-dimensional integrated circuits |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
DELTA
2002
IEEE
14 years 22 days ago
2002
IEEE
Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry...
ITC
1996
IEEE
13 years 12 months ago
1996
IEEE
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
ASPDAC
1998
ACM
14 years 3 hour ago
1998
ACM
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...