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CHES
2006
Springer
134views Cryptology» more  CHES 2006»
14 years 24 days ago
Read-Proof Hardware from Protective Coatings
In cryptography it is assumed that adversaries only have black box access to the secret keys of honest parties. In real life, however, the black box approach is not sufficient beca...
Pim Tuyls, Geert Jan Schrijen, Boris Skoric, Jan v...
MICRO
2009
IEEE
103views Hardware» more  MICRO 2009»
14 years 3 months ago
BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support
A platform that supported Sequential Consistency (SC) for all codes — not only the well-synchronized ones — would simplify the task of programmers. Recently, several hardware ...
Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Tor...
IPPS
2008
IEEE
14 years 3 months ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
IPPS
2007
IEEE
14 years 3 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
14 years 2 months ago
Automated silicon debug data analysis techniques for a hardware data acquisition environment
Abstract—Silicon debug poses a unique challenge to the engineer because of the limited access to internal signals of the chip. Embedded hardware such as trace buffers helps overc...
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas...