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MTA
2011
203views Hardware» more  MTA 2011»
13 years 5 months ago
Interoperable digital rights management based on the MPEG Extensible Middleware
Abstract This paper describes an interoperable Digital Rights Management architecture promoted by the MPEG standardization group in its new standard known as MPEG-M or MPEG Extensi...
Víctor Rodríguez-Doncel, Jaime Delga...
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
14 years 7 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
DATE
2007
IEEE
117views Hardware» more  DATE 2007»
14 years 5 months ago
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in in...
Shweta Srivastava, Jaijeet S. Roychowdhury
ISQED
2007
IEEE
128views Hardware» more  ISQED 2007»
14 years 5 months ago
A Model for Timing Errors in Processors with Parameter Variation
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 4 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler