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» Time Management in The High Level Architecture
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DAC
2006
ACM
14 years 9 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
HPCA
2006
IEEE
14 years 9 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
SIGARCH
2008
107views more  SIGARCH 2008»
13 years 8 months ago
A lightweight streaming layer for multicore execution
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
David Zhang, Qiuyuan J. Li, Rodric Rabbah, Saman A...
CLEIEJ
2006
169views more  CLEIEJ 2006»
13 years 8 months ago
Tailoring RUP for LMS Selection: A Case Study
Learning Management System (LMS) development has become a high priority project for educational institutions and organizations, as it provides the virtual environment for online e...
Luis Eduardo Mendoza, María A. Pérez...
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
14 years 2 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...