769 search results - page 101 / 154 » Timed Circuit Synthesis Using Implicit Methods |
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
In this paper, we propose a new circuit transformation technique in conjunction with the use of a special diagnostic test pattern, named SO-SLAT pattern, to achieve higher multipl...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
ASPDAC
2000
ACM
14 years 2 months ago
2000
ACM
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
ITC
1996
IEEE
14 years 2 months ago
1996
IEEE
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
This paper presents a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifier...