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» Timed Circuit Synthesis Using Implicit Methods
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ISQED
2005
IEEE
169views Hardware» more  ISQED 2005»
14 years 1 months ago
ASLIC: A Low Power CMOS Analog Circuit Design Automation
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Jihyun Lee, Yong-Bin Kim
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 12 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
DAC
1998
ACM
13 years 12 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
DAC
2009
ACM
14 years 8 months ago
BDD-based synthesis of reversible logic for large functions
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-pow...
Robert Wille, Rolf Drechsler
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
14 years 1 months ago
A practical method to estimate interconnect responses to variabilities
Variabilities in metal interconnect structures can affect circuit timing performance or even cause function failure in VLSI designs. This paper proposes a method to estimate the ...
Frank Liu