769 search results - page 81 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ISLPED
1996
ACM
14 years 2 months ago
1996
ACM
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...
MJ
2007
13 years 9 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
DSD
2005
IEEE
14 years 3 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
DAC
2006
ACM
14 years 11 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
RTSS
2000
IEEE
14 years 2 months ago
2000
IEEE
The maturity of schedulabilty analysis techniquesfor fired-prioritypreemptive scheduling has enabled the consideration of timing issues at design time using a specification of the...