4306 search results - page 136 / 862 » Timed Testing with TorX |
ATS
2002
IEEE
14 years 3 months ago
2002
IEEE
As the deep sub-micron techniques evolving, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to the access limitations. ...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
ATS
2009
IEEE
14 years 5 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
VTS
2005
IEEE
14 years 3 months ago
2005
IEEE
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...