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MTV
2005
IEEE
101views Hardware» more  MTV 2005»
14 years 3 months ago
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
Semiconductor manufacturers aim at deliver new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time...
Paolo Bernardi, Michelangelo Grosso, Maurizio Reba...
ITC
2002
IEEE
102views Hardware» more  ITC 2002»
14 years 3 months ago
Fault Grading FPGA Interconnect Test Configurations
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin T...
ICRA
2010
IEEE
120views Robotics» more  ICRA 2010»
13 years 8 months ago
Approximation of feasibility tests for reactive walk on HRP-2
— We present here an original approach to test the feasibility of footsteps for a given walking pattern generator. It is based on a new approximation algorithm intended to cope w...
Nicolas Perrin, Olivier Stasse, Florent Lamiraux, ...
DATE
2008
IEEE
84views Hardware» more  DATE 2008»
14 years 4 months ago
Physically-Aware N-Detect Test Pattern Selection
N-detect test has been shown to have a higher likelihood for detecting defects. However, traditional definitions of Ndetect test do not necessarily exploit the localized characte...
Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D...
FCT
2003
Springer
14 years 3 months ago
An Extended Quadratic Frobenius Primality Test with Average and Worst Case Error Estimates
We present an Extended Quadratic Frobenius Primality Test (EQFT), which is related to the Miller-Rabin test and to several other known probabilistic tests. EQFT takes time equival...
Ivan Damgård, Gudmund Skovbjerg Frandsen