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SIGCSE
2004
ACM
99views Education» more  SIGCSE 2004»
14 years 4 months ago
Java IO and testing made simple
We present software tools that support robust input processing and comprehensive testing in Java. The software includes the JPT library that supports error-checked typed input via...
Viera K. Proulx, Richard Rasala
DFT
2000
IEEE
105views VLSI» more  DFT 2000»
14 years 3 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
DFT
1999
IEEE
75views VLSI» more  DFT 1999»
14 years 3 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 7 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
DATE
2009
IEEE
93views Hardware» more  DATE 2009»
14 years 5 months ago
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Ha...