53 search results - page 4 / 11 » Timing driven maze routing |
DAC
1994
ACM
14 years 1 months ago
1994
ACM
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
GLVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
-- This paper presents a novel global routing algorithm, AT-PO-GR, to minimize the routing area under both congestion, timing, and RLC crosstalk constraints. The proposed algorithm...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
FPGA
1999
ACM
14 years 1 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...