264 search results - page 16 / 53 » Timing driven power gating |
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
ISPD
2012
ACM
12 years 4 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...