264 search results - page 6 / 53 » Timing driven power gating |
VLSID
2002
IEEE
14 years 1 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
TCAD
2008
13 years 8 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
ISPD
2000
ACM
14 years 29 days ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
ISCAS
1999
IEEE
14 years 27 days ago
1999
IEEE
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Power gating has been widely adopted in multicore designs. The design of fast and reliable power mode transition for per-core power gating remains a challenging problem. This paper...