120 search results - page 7 / 24 » Timing-driven placement for FPGAs |
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
FPGA
2000
ACM
13 years 11 months ago
2000
ACM
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...