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» Topological Design of Interconnected LAN-MAN Networks
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MSS
2005
IEEE
131views Hardware» more  MSS 2005»
14 years 1 months ago
Impact of Failure on Interconnection Networks for Large Storage Systems
Recent advances in large-capacity, low-cost storage devices have led to active research in design of large-scale storage systems built from commodity devices for supercomputing ap...
Qin Xin, Ethan L. Miller, Thomas J. E. Schwarz, Da...
EUROPAR
2005
Springer
14 years 1 months ago
INSEE: An Interconnection Network Simulation and Evaluation Environment
In this paper we introduce INSEE, an environment to help in the design of interconnection networks for parallel computing systems. It contains two basic modules: a system to genera...
Francisco Javier Ridruejo Perez, José Migue...
HPCA
2003
IEEE
14 years 8 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
NOCS
2010
IEEE
13 years 5 months ago
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna...
DATE
2005
IEEE
108views Hardware» more  DATE 2005»
14 years 1 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik