104 search results - page 2 / 21 » Toward effective utilization of timing exceptions in design ... |
CODES
2003
IEEE
14 years 21 days ago
2003
IEEE
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
ASAP
2003
IEEE
14 years 21 days ago
2003
IEEE
There is a growing demand for application-specific embedded processors in system-on-a-chip designs. Current tools and design methodologies often require designers to manually spec...
VIS
2009
IEEE
14 years 8 months ago
2009
IEEE
We develop a new algorithm for isosurface extraction and view-dependent filtering from large time-varying fields, by using a novel Persistent Time-Octree (PTOT) indexing structure....
ISPD
2000
ACM
13 years 11 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...