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» Towards Nanoelectronics Processor Architectures
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DATE
2008
IEEE
75views Hardware» more  DATE 2008»
14 years 2 months ago
A low-cost concurrent error detection technique for processor control logic
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
SIPS
2008
IEEE
14 years 1 months ago
The support of software design patterns for streaming RPC on embedded multicore processors
The development of embedded system has been toward the multicore architectures in the recent years. It raises concerns in the community of supporting programming models and langua...
Kun-Yuan Hsieh, Yen-Chih Liu, Chi-Hua Lai, Jenq Ku...
HPCA
2009
IEEE
14 years 8 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 4 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
ASPLOS
2012
ACM
12 years 3 months ago
DreamWeaver: architectural support for deep sleep
Numerous data center services exhibit low average utilization leading to poor energy efficiency. Although CPU voltage and frequency scaling historically has been an effective mea...
David Meisner, Thomas F. Wenisch