44 search results - page 5 / 9 » Trace-Level Speculative Multithreaded Architecture |
HPCA
1998
IEEE
13 years 10 months ago
1998
IEEE
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
ICS
2009
Tsinghua U.
14 years 1 months ago
2009
Tsinghua U.
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
This paper introduces a novel technique which leverages value prediction and multithreading on a simultaneous multithreading processor to achieve higher performance in a single th...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
HPCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Performance of multithreaded programs is heavily influenced by the latencies of the thread management and synchronization operations. Improving these latencies becomes especially...