639 search results - page 16 / 128 » Tradeoffs in designing accelerator architectures for visual ... |
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
IEEEHPCS
2010
13 years 7 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
HUC
2003
Springer
14 years 2 months ago
2003
Springer
With increased use of mobile information technology and increased amounts of information comes the need to simplify information presentation. This research considers whether low-in...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
TOMACS
1998
13 years 8 months ago
1998
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...