639 search results - page 7 / 128 » Tradeoffs in designing accelerator architectures for visual ... |
161
Voted
DAC
2004
ACM
15 years 7 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
170
Voted
ASAP
2006
IEEE
15 years 9 months ago
2006
IEEE
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
135
Voted
DAC
2003
ACM
16 years 4 months ago
2003
ACM
This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents t...
151
Voted
IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
110
Voted
DAC
2002
ACM
16 years 4 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...