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» Transliteration as Constrained Optimization
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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 14 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
14 years 8 days ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
13 years 11 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
ECBS
1999
IEEE
138views Hardware» more  ECBS 1999»
13 years 11 months ago
Multi-Domain Surety Modeling and Analysis for High Assurance Systems
Engineering systems are becoming increasingly complex as state of the art technologies are incorporated into designs. Surety modeling and analysis is an emerging science which per...
James Davis, Jason Scott, Janos Sztipanovits, Marc...
SIGGRAPH
1999
ACM
13 years 11 months ago
A Hierarchical Approach to Interactive Motion Editing for Human-Like Figures
This paper presents a technique for adapting existing motion of a human-like character to have the desired features that are specified by a set of constraints. This problem can b...
Jehee Lee, Sung Yong Shin