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» Tutorial: Design of a Logic Synthesis System
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ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
13 years 11 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
POPL
2005
ACM
14 years 7 months ago
Synthesis of interface specifications for Java classes
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
P. Madhusudan, Pavol Cerný, Rajeev Alur, Wo...
AADEBUG
2005
Springer
14 years 27 days ago
An integrated debugging environment for reprogrammble hardware systems
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...
Kevin Camera, Hayden Kwok-Hay So, Robert W. Broder...
DAC
2007
ACM
14 years 8 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
FPL
2004
Springer
205views Hardware» more  FPL 2004»
14 years 22 days ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...