524 search results - page 11 / 105 » Two efficient methods to reduce power and testing time |
ET
2002
13 years 7 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
We consider self-testing of complete wireless nodes in the field through a low-energy software-based selftest (SBST) method. Energy consumption is optimized both for individual co...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
—A computationally efficient optimal discrete bit allocation algorithm is proposed for medium and high target bit rate discrete multitone (DMT) transmissions. Unlike conventional...