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ACSD
2005
IEEE
121views Hardware» more  ACSD 2005»
14 years 2 months ago
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...
Matthieu Moy, Florence Maraninchi, Laurent Maillet...
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
14 years 1 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 5 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
14 years 1 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
DAC
2001
ACM
14 years 9 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra