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ISCA
1997
IEEE
103views Hardware» more  ISCA 1997»
15 years 6 months ago
Designing High Bandwidth On-Chip Caches
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
Kenneth M. Wilson, Kunle Olukotun
CIKM
1994
Springer
15 years 6 months ago
Intelligent Caching: Selecting, Representing, and Reusing Data in an Information Server
Accessing information sources to retrieve data requested by a user can be expensive, especially when dealing with distributed information sources. One way to reduce this cost is t...
Yigal Arens, Craig A. Knoblock
ICCAD
1997
IEEE
162views Hardware» more  ICCAD 1997»
15 years 6 months ago
Application-driven synthesis of core-based systems
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
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DATE
2004
IEEE
159views Hardware» more  DATE 2004»
15 years 6 months ago
Compositional Memory Systems for Data Intensive Applications
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
15 years 9 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...