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117
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ICON
2007
IEEE
15 years 9 months ago
A Cache Architecture for Counting Bloom Filters
— Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., u...
Mahmood Ahmadi, Stephan Wong
92
Voted
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
15 years 6 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
CASES
2005
ACM
15 years 4 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
145
Voted
ASPLOS
2006
ACM
15 years 8 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
ISCA
2002
IEEE
159views Hardware» more  ISCA 2002»
15 years 7 months ago
Avoiding Initialization Misses to the Heap
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black