Sciweavers

1052 search results - page 25 / 211
» Understanding POWER multiprocessors
Sort
View
RTCSA
2000
IEEE
14 years 23 hour ago
Fixed-priority preemptive multiprocessor scheduling: to partition or not to partition
Traditional multiprocessor real-time scheduling partitions a task set and applies uniprocessor scheduling on each processor. By allowing a task to resume on another processor than...
Björn Andersson, Jan Jonsson
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 12 months ago
Transformational partitioning for co-design of multiprocessor systems
This paper presents the underlying methodology of Cosmos, an interactive approach for hardware software co-design capable of handling multiprocessor systems and distributed archit...
Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ah...
3DIC
2009
IEEE
263views Hardware» more  3DIC 2009»
13 years 11 months ago
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwa...
DAC
1999
ACM
13 years 12 months ago
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
14 years 1 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...