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» Unified decoder architecture for LDPC turbo codes
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VTC
2008
IEEE
124views Communications» more  VTC 2008»
14 years 2 months ago
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...
Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien
ASAP
2006
IEEE
108views Hardware» more  ASAP 2006»
13 years 11 months ago
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
Pablo Ituero, Marisa López-Vallejo
ICCD
2006
IEEE
275views Hardware» more  ICCD 2006»
14 years 4 months ago
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
Tinoosh Mohsenin, Bevan M. Baas
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
13 years 9 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
14 years 1 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...