65 search results - page 7 / 13 » Unified decoder architecture for LDPC turbo codes |
ASAP
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
DATE
2002
IEEE
14 years 18 days ago
2002
IEEE
Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s sys...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...
ISCAS
2003
IEEE
14 years 27 days ago
2003
IEEE
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
TVLSI
2002
13 years 7 months ago
2002
Abstract--The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is requir...