Sciweavers

720 search results - page 72 / 144
» Uniform Memory Hierarchies
Sort
View
156
Voted
DAC
2002
ACM
16 years 5 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
160
Voted
ASPLOS
2006
ACM
15 years 10 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
FOCS
2000
IEEE
15 years 9 months ago
Cache-Oblivious B-Trees
We present dynamic search-tree data structures that perform well in the setting of a hierarchical memory (including various levels of cache, disk, etc.), but do not depend on the ...
Michael A. Bender, Erik D. Demaine, Martin Farach-...
SIGMETRICS
1996
ACM
118views Hardware» more  SIGMETRICS 1996»
15 years 8 months ago
Integrating Performance Monitoring and Communication in Parallel Computers
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
Margaret Martonosi, David Ofelt, Mark Heinrich
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
15 years 4 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...