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DAC
2004
ACM
14 years 8 months ago
Abstraction of assembler programs for symbolic worst case execution time analysis
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...
Klaus Schneider, Tobias Schüle
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
14 years 25 days ago
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...
Abhik Roychoudhury, Tulika Mitra, S. R. Karri
ISCOPE
1999
Springer
13 years 11 months ago
Using Object-Oriented Techniques for Realizing Parallel Architectural Skeletons
The concept of design patterns has recently emerged as a new paradigm in the context of object-oriented design methodology. Similar ideas are being explored in other areas of compu...
Dhrubajyoti Goswami, Ajit Singh, Bruno R. Preiss
JUCS
2010
130views more  JUCS 2010»
13 years 2 months ago
Toward an Integrated Tool Environment for Static Analysis of UML Class and Sequence Models
: There is a need for more rigorous analysis techniques that developers can use for verifying the critical properties in UML models. The UML-based Specification Environment (USE) t...
Wuliang Sun, Eunjee Song, Paul C. Grabow, Devon M....
DAC
2002
ACM
14 years 8 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...