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ICCD
2008
IEEE
119views Hardware» more  ICCD 2008»
14 years 4 months ago
Hierarchical simulation-based verification of Anton, a special-purpose parallel machine
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
John P. Grossman, John K. Salmon, Richard C. Ho, D...
DAC
2010
ACM
13 years 11 months ago
Circuit modeling for practical many-core architecture design exploration
Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the multiple processor archi...
Dean Truong, Bevan M. Baas
EIT
2009
IEEE
14 years 2 months ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
Zhongbo Cao, Ramon Mercado, Diane T. Rover
CODES
2004
IEEE
13 years 11 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
DSD
2009
IEEE
124views Hardware» more  DSD 2009»
14 years 2 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...