122 search results - page 14 / 25 » User-controllable coherence for high performance shared memo... |
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
CCGRID
2006
IEEE
14 years 3 months ago
2006
IEEE
A problem with running distributed shared memory applications in heterogeneous environments is that making optimal use of available resources often requires significant changes t...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
SRDS
1994
IEEE
14 years 1 months ago
1994
IEEE
Most recovery schemes that have been proposed for Distributed Shared Memory (DSM) systems require unnecessarily high checkpointing frequency and checkpoint traffic, which are sens...